(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit having a phase locked loop and, more particularly, to a circuit structure for testing the phase locked loop.
(b) Description of the Related Art
A semiconductor integrated circuit, such as a logic LSI, generates an internal clock signal having a higher frequency than an input clock signal to operate the internal circuit thereof, such as a microprocessor or digital signal processor. For this purpose, a phase locked loop is generally used which multiplies the frequency of the input clock signal to provide the higher frequency clock signal which is in synchrony with the input clock signal. Some phase locked loops operate in an analog format, and it is generally important to test the phase locked loop by using a logic tester or analog tester to evaluate the characteristics of the phase locked loop.
FIG. 1 shows a conventional analog phase locked loop 13 incorporated in a logic LSI 11, which is under an evaluation test by a logic tester 29. The logic LSI 11 comprises an internal circuit 12 and a phase locked loop 13 for supplying an internal clock signal 104 to the internal circuit 12. The phase locked loop 13 comprises a phase comparator 15 for comparing an internal signal 105 against an input clock signal, a low-pass filter 16 receiving an analog output from the phase comparator 15, a voltage controlled oscillator (VCO) 17 controlled by an output 102 from the low-pass filter 16 to supply an internal clock signal 104 to the internal circuit 12, and a frequency divider 18 for dividing the frequency of an output 104 from the VCO 17 to provide the internal signal 105 to the comparator 15.
In a normal operation mode of the logic LSI 11, an input clock signal is supplied to the phase comparator 15, which outputs a phase difference signal representing the phase difference between the input clock signal and the internal signal 105 through the low-pass filter 16 to the VCO 17. The VCO 17 is controlled by the output 102 of the low-pass filter 16 to supply the internal clock signal 104 having a multiplied frequency which is a product of frequency of the input clock signal by a multiplication factor equal to the dividing ratio by the frequency divider 18.
In the evaluation test mode of the logic LSI 11, a driver 31 in the logic tester 29 supplies a test clock signal 101 to the phase comparator 15 of the phase locked loop 13. The output clock signal 104 of the VCO 17 is supplied to a comparator 30 of the logic tester 29, which evaluates the output clock signal 104 by judging whether or not the level of the output clock signal 104 resides within an expected range at a specified timing.
FIG. 2 shows a timing chart for the test mode of the logic LSI 11, wherein three examples for the test output signal 104, which are obtained by multiplication of the frequency of the test clock signal 101 by two, are shown together with the test clock signal 101. The timing chart also shows the specified timing of the evaluation for each of the examples by an arrow, as well as the results of the judgement in the examples, namely, "pass" or "fail". The first example shows a "pass" wherein the level of each clock pulse is judged to be correct at each specified timing, and the second example shows a "fail" wherein some clock pulses are judged to be incorrect because of the incorrect frequency of the output clock signal 104, which may cause a malfunction of the internal circuit 12.
The third example shows a "fail" determined by the logic tester 29 wherein the level of each clock pulse is judged to be incorrect, although the output clock frequency itself is correct and, therefore, there is no possible malfunction in the internal circuit 12 caused by the judged incorrect level of each clock pulse.
The logic LSI 11 of FIG. 1 can be tested also by an analog test circuit including an oscillator and a voltmeter such as shown in FIG. 3, as described in Utility Model Kokai Publication 2-32078. The oscillator 20 supplies a test clock signal 101 to the phase comparator 15, as in the case of the logic tester of FIG. 1, and the voltmeter 19 determines the voltage level of the output 102 of the low-pass filter 16 controlling the output frequency from the VCO 17.
FIG. 4 is a typical graph for showing the output frequency of the VCO against the output voltage of the low-pas filter, i.e., input control voltage of the VCO. The output frequency monotonically increases from a minimum frequency f.sub.min to a maximum frequency f.sub.max with the increase of the input control voltage of the VCO. Especially in the range between VB and VA, the VCO operates in a stable and normal state so that the output frequency is determined by the input control voltage. In the graph, assuming that the design frequency of the VCO 17 is f.sub.x and the dividing factor by the divider 18 is 1/2 in the example of FIG. 3, a frequency of f.sub.x /2 is supplied as the input test clock signal 101 from the oscillator 20. In this case, if the input control voltage (VX) resides between VB and VA, as shown in FIG. 5, the phase locked loop 13 operates in a stable and normal state. On the other hand, if the input control voltage (VX') does not reside between VB and VA, as shown in FIG. 5, the phase locked loop 13 does not operate in a stable and normal state. Namely, by measuring the input control voltage of the VCO 17, the phase locked loop 13 can be evaluated in its operation.
In the evaluation by the analog tester of FIG. 3, it is to be noted that if the voltmeter 19 has an input impedance comparable with or lower than the output impedance of the low-pass filter 16 or the input impedance of the internal circuit 12, the measurement by the voltmeter 19 is not satisfactory in its reliability. Accordingly, voltmeter 19 must have a sufficiently high input impedance to obtain a reliable result for the evaluation test.